FIG. 23 shows the arrangement of a conventional clock/data recovery circuit. FIG. 24 shows its detailed arrangement. This clock/data recovery circuit is disclosed in, e.g., reference “M. Nogawa, et al., “A 10 Gb/s Burst-Mode CDR IC in 0.13 μm CMOS”, ISSCC 2005 Dig. Tech. Papers, PP. 228-229, FIG. 12.5.4.”
The conventional clock/data recovery circuit includes a clock recovery circuit 100 and a data decision circuit 200. For example, as shown in FIG. 24, the clock recovery circuit 100 includes a gating circuit 110 and a gated VCO (Voltage Controlled Oscillator) 120. The gating circuit 110 includes a buffer 111, a delay circuit 112, and a NAND circuit 113. The gated VCO 120 includes inverters 121 and 122 and a NAND circuit 123. The gating circuit 110 detects the rising edge of input data DIN. The gated VCO 120 generates a recovered clock RCK in phase with the rising edge of the input data DIN. The data decision circuit 200 is formed from a D flip-flop circuit.
The operation of the conventional clock/data recovery circuit will be described with reference to FIGS. 25A to 25C and 26A to 26C. FIGS. 25A to 25C show a case in which the duty of the input data DIN is 100%, and the conventional clock/data recovery circuit operates normally. The gating circuit 110 generates a pulse having a width of ½ UI (Unit Interval) at the rising edge of the input data DIN shown in FIG. 25A and inputs it to the NAND circuit 123 of the gated VCO 120, thereby making the phase of the recovered clock RCK match that of the input data DIN. As a result, the clock recovery circuit 100 outputs the recovered clock RCK in phase with the rising edge of the input data DIN (FIG. 25B). The data decision circuit 200 receives the input data DIN via a data input terminal D of the flip-flop circuit and the recovered clock RCK via a clock input terminal CK. The recovered clock RCK is in phase with the input data DIN. The flip-flop circuit included in the data decision circuit 200 shapes the waveform of the input data DIN starting from the falling edge of the recovered clock RCK and outputs recovered output data DOUT from an output terminal Q (FIG. 25C).